1. Field of the Invention
This invention relates to components for electronic packages having integral bumps. More particularly, leadframes and package bases contain unitary protrusions for electrical interconnection to external circuitry.
2. Description of Related Art
Microelectronic devices are typically manufactured from a semiconductor material such as silicon, germanium or gallium/arsenide. The semiconductor material is fashioned into a die, a generally rectangular structure having circuitry formed on one surface. Along the periphery of that electrically active surface are input/output pads to facilitate electrical interconnection to external circuitry.
The semiconductor device is brittle and requires protection from moisture and mechanical damage. This protection is provided by an electronic package. The electronic package further contains an electrically conductive means to transport electrical signals between the semiconductor device and the external circuitry.
One electronic package is disclosed in U.S. Pat. No. 4,939,316 to Mahulikar et al. which is incorporated by reference in its entirety herein. The patent discloses separate anodized aluminum or aluminum alloy base and cover components defining a cavity. A leadframe is disposed between the base and the cover and adhesively bonded to both. A semiconductor device is encased within the cavity and electrically interconnected to the inner lead ends of the leadframe. The outer lead ends of the leadframe extend beyond the package perimeter and are interconnected to external circuitry.
A similar electronic package having an anodized aluminum or aluminum alloy base component and a cover formed from a material other than aluminum is disclosed in U.S. Pat. No. 5,155,299 to Mahulikar et al.
The available space on a printed circuit board is limited and it is desirable to minimize the peripheral area of a package. The peripheral area of a leaded package extends beyond the perimeter of the package base and cover to a point defined by the outer lead portions of the leadframe.
To minimize the peripheral area of an electronic package, electrical interconnection may be through the base of a package. One such electronic package is disclosed in U.S. Pat. No. 4,965,227 to Chang et al. A plurality of terminal pins support and are electrically interconnected to a flexible metal tape formed into a desired circuit pattern. One end of the terminal pins, the flexible metal circuit and a semiconductor device are then encapsulated in a molding resin. The molding resin defines the package perimeter with the unencapsulated end of the terminal pins extending outward from the package base.
The terminal pins are thin, 0.020 inch diameter copper, as an example, and may be up to 0.5 inch long. The pins are prone to bending and care is required to maintain pin alignment. The pins are plugged into mating holes on a printed circuit board. Care is also required when drilling the holes to insure an accurate fit.
A cross between a leaded package and a pin grid array package is disclosed in U.S. Pat. No. 4,677,526 to Muehling. The outer leads of a leadframe are bent to a 90.degree. angle relative to the plane defined by the inner leads. The inner leads and a semiconductor device are encapsulated in a molding resin with the outer lead portions extending through the package base.
A disadvantage with this package is that the radius of curvature is dependent on the leadframe material and the temper of that material. If the radius is formed too tightly, the leadframe material may crack or "orange peel". Generally, the ratio of the minimum bend radius to the leadframe thickness, mbr/t, is between about 1 and 2 for copper alloy leadframes. A 0.010 inch thick leadframe requires a radius of curvature of at least 0.010 inch to prevent lead fracture.
Metallic solder pads and solder balls are used in a ball grid array and land grid array packages as disclosed in U.S. Pat. No. 5,241,133 to Mullen, III et al. The patent discloses an electronic package having an insulating substrate with circuit traces on a first side and a uniform array of solder pads on an opposing second side. A semiconductor device is mounted to the first side of the substrate and electrically interconnected to the circuit traces. Conductive vias electrically interconnect the circuit traces and the solder pads. A molded plastic cover encapsulates the device and inner lead ends.
A ball grid array package having a metallic base is disclosed in U.S. patent application Ser. No. 08/033,596 entitled "Ball Grid Array Electronic Package" by Mahulikar et al., filed Mar. 19, 1993. A metallic base component has an array of holes. The walls of the holes are electrically nonconductive. If, for example, the base is aluminum or an aluminum alloy, the hole walls are made nonconductive by anodization. Terminal pins, a solder or a conductive adhesive extend through the holes terminating approximately in the plane defined by the outside surface of the base.
A problem with ball grid array packages is the coefficient of thermal expansion (C.T.E.) mismatch between the semiconductor package and a printed circuit board causes the solder balls to be extended or compressed with temperature variations. This flexing fatigues the solder balls and eventually causes failure of the solder joint.
A solution to solder fatigue is disclosed in U.S. Pat. No. 4,581,680 to Garner. Metallization pads are formed in recesses on the package base. The depth of the recesses increases with the distance between the recess and the center of the package base. Longer length solder joints around the periphery of the package provide improved flexibility to compensate for the C.T.E. mismatch.
There exists, however, a need for an improved leadframe having outer leads perpendicular to the inner leads. There exists also a need for a ball grid array electronic package or land grid array electronic package that reduces solder fatigue